6 5 $ 0 copyright ?1998 alliance semiconductor. all rights reserved. ? $ 6 & $ 6 & ', ',' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 9 9 . e & 0 2 6 6 5 $ 0 )hdwxuhv ? organization: 32,768 words 16 bits ? high speed - 10/12/15/20 ns address access time - 5/6/8/10 ns output enable access time ? low power consumption - active: 504 mw max (20 ns cycle) - standby: 18 mw max, cmos i/o - very low dc component in active power ? 2.0v data retention ? equal access and cycle times ? easy memory expansion with ce , oe inputs ? ttl-compatible, three-state i/o ? 44-pin jedec standard package - 400 mil soj - 400 mil tsop ii ? upward compatibility - 64k16 (as7c1026) - 256k16 (as7c4098) ? center power and ground pins ? esd protection 3 2000 volts ? latch-up current 3 200 ma ? 3.3v version available (as7c3513) /rjlfeorfngldjudp 32k 16 array oe ce we column decoder row decoder a0 a1 a2 a3 a4 a5 a7 vcc gnd a8 a9 a10 a11 a12 a13 a14 control circuit i/o0Ci/o7 i/o8Ci/o15 ub lb i/o buffer a6 3lqduudqjhphqw 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o13 i/o12 gnd v cc i/o11 i/o10 i/o9 i/o8 nc a7 a8 a9 a10 nc a0 ce i/o0 i/o1 i/o2 i/o3 v cc gnd i/o4 i/o5 i/o6 i/o7 we a14 a13 a12 soj, tsop ii 21 22 a11 nc ub lb i/o15 i/o14 2 a3 3 a2 4 a1 1 nc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a5 a6 oe a4 6hohfwlrq?jxlgh shaded areas indicate advance information. 7c513-10 7c3513-10 7c513-12 7c3513-12 7c513-15 7c3513-15 7c513-20 7c3513-20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 5 5 8 10 ns maximum operating current AS7C513 170 160 150 140 ma as7c3513 130 120 110 100 ma maximum cmos standby current 5555ma
6 5 $ 0 $ 6 & $ 6 & ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ' ', ,' ' $ $ )xqfwlrqdoghvfulswlrq the AS7C513 is a high performance cmos 524,288-bit static random access memory (sram) organized as 32,768 words 16 bits. it i s designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5/6/8/10 ns are ideal for high performance applications. the chip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the AS7C513 is guaranteed not to exceed 28 mw power consumption in cmos standby mode. this device also offers 2.0v data retention. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o0-i/o15 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive, or write enable is ac tive, output drivers stay in high-impedance mode. this device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o0Ci/o7, and ub controls the higher bits, i/o8Ci/o15. all chip inputs and outputs are ttl-compatible, and operation is from a single 5v supply. the AS7C513 is packaged in common ind ustry standard packages. $evroxwhpd[lpxpudwlqjv note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 7uxwkwdeoh key: x = dont care, l = low, h = high parameter symbol min max unit voltage on any pin relative to gnd v t C1 +7.0 v power dissipation p d C1.0w storage temperature (plastic) t stg C55 +150 o c temperature under bias t bias C10 +85 o c dc output current i out C50ma ce we oe lb ub i/o0Ci/o7 i/o8Ci/o15 mode h x x x x high z high z standby lhllhd out high z read i/o0Ci/o7 lhlhlhigh zd out read i/o8Ci/o15 lhllld out d out read i/o0Ci/o15 llxlld in d in write i/o0Ci/o15 llxlhd in high z write i/o0Ci/o7 llxhlhigh zd in write i/o8Ci/o15 l l h x h x x h x h high z high z output disable
6 5 $ 0 ? $ 6 & $ 6 & ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 6 5 $ 0 5hfrpphqghgrshudwlqjfrqglwlrqv ? v il min = C3.0v for pulse width less than t rc /2. '&rshudwlqjfkdudfwhulvwlfv shaded areas indicate advance information. &dsdflwdqfh parameter symbol min typ max unit supply voltage AS7C513 v cc 4.5 5.0 5.5 v as7c3513 v cc 3.0 3.3 3.6 v gnd 0.0 0.0 0.0 v input voltage AS7C513 v ih 2.2 C v cc + 0.5 v as7c3513 v ih 2.0 C v cc + 0.5 v il C0.5 ? C0.8v ambient operating temperature t a 0- 70c parameter symbol test conditions -10 -12 -15 -20 unit min max min max min max min max input leakage current | i li | 0v v in v cc -5 5-55-55-55 a output leakage current | i lo | outputs disabled 0v v out v cc -5 5-55-55-55 a operating power supply current i cc ce v il , v cc = max outputs open, f = f max = 1/t rc AS7C513 C 170 C 160 C 150 C 140 ma as7c3513 C 130 C 120 C 110 C 100 standby power supply current i sb ce v il , v cc = max outputs open, f = f max = 1/t rc C 70 C 60 C 50 C 40 ma i sb1 ce 3 v cc C0.2v, v cc = max, v in gnd + 0.2v or v in 3 v cc - 0.2v, f = 0 C 5C5C5C5ma output voltage v ol i ol = 8 ma, v cc = min C 0.4 C 0.4 C 0.4 C 0.4 v v oh i oh = C4 ma, v cc = min 2.4 C2.4C2.4C2.4C v parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe , lb , ub v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
6 5 $ 0 $ 6 & $ 6 & ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ' ', ,' ' $ $ 5hdgf\foh 3,9 shaded areas indicate advance information. 5hdgzdyhirup 3,6,7,9 5hdgzdyhirup 3,6,8,9 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max read cycle time t rc 10 C12C15C20Cns address access time t aa C 10 C 12 C 15 C 20 ns 3 chip enable (ce ) access time t ace C 10 C 12 C 15 C 20 ns 3 output enable (oe ) access time t oe C 5C5C8C10ns output hold from address change t oh 3 C3C4C4Cns5 ce low to output in low z t clz 0 C0C0C0Cns4, 5 ce high to output in high z t chz C 5C6C6C8ns4, 5 oe low to output in low z t olz 0 C0C0C0Cns4, 5 byte select access time t ba C 5C6C8C10ns byte select low to low-z t blz 0 C0C0C0Cns4,5 byte select high to high-z t bhz C 5C6C6C8ns4,5 oe high to output in high z t ohz C 5C6C6C8ns4, 5 power up time t pu 0 C0C0C0Cns4, 5 power down time t pd C 10 C 12 C 15 C 20 ns 4, 5 t oh t aa t rc t oh data out address data valid previous data valid data valid t rc t aa t blz t ba t oe t olz t oh t ohz t hz t bhz t ace t lz address oe ce lb , ub data out
6 5 $ 0 ? $ 6 & $ 6 & ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 6 5 $ 0 :ulwhf\foh 11 shaded areas indicate advance information. :ulwhzdyhirup 10,11 :ulwhzdyhirup 10,11 parameter symbol -10-12-15-20 unit notes min max min max min max min max write cycle time t wc 10 C12C15C20C ns chip enable (ce ) to write end t cw 8 C9C10C13C ns address setup to write end t aw 7 C8C10C12C ns address setup time t as 0 C0C0C0C ns write pulse width t wp 7 C8C10C12C ns address hold from end of write t ah 0 C0C0C0C ns data valid to write end t dw 5 C6C8C10C ns data hold time t dh 0 C0C0C0C ns 5 write enable to output in high z t wz C 5C6C6C8 ns 4, 5 output active from write end t ow 3 C3C3C3C ns 4, 5 byte select low to end of write t bw 7 C9C9C12C ns address ce lb , ub we data in data out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t ah data undefined high-z data valid address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t ow t wz t ah data out data undefined high-z high-z t as t aw data valid t clz
6 5 $ 0 $ 6 & $ 6 & ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ' ', ,' ' $ $ 'dwduhwhqwlrqfkdudfwhulvwlfv 'dwduhwhqwlrqzdyhirup $&whvwfrqglwlrqv 1rwhv 1 during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled and not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, c. 4 these parameters are specified with c l = 5pf as in figure c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce or we must be high during address transitions. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce 3 v cc C0.2v v in 3 v cc C0.2v or v in 0.2v 2.0 C v data retention current i ccdr C 500 m a chip deselect to data retention time t cdr 0Cns operation recovery time t r t rc Cns input leakage current | i li | C1 m a v cc ce t r t cdr data retention mode 4.5v or 3.0v 4.5v or 3.0v v dr 3 2.0v v ih v ih v dr 255 w 5 pf* 480 w d out gnd +5v figure c: output load for t clz , t chz , - output load: see figure b, except as noted. - input pulse level: gnd to 3.0v. see figure a. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 168 w thevenin equivalent: d out +1.728v 255 w 30 pf* 480 w d out gnd +5v figure b: output load *including scope 10% 90% 10% 90% gnd +3.0v and jig capacitance figure a: input pulse t olz , t ohz , t ow 2ns
6 5 $ 0 ? $ 6 & $ 6 & ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 6 5 $ 0 7\slfdo'&dqg$&fkdudfwhulvwlfv supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature (c) C55 80 125 35 C10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature (c) -55 80 125 35 -10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = 5.0v supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature (c) C55 80 125 35 C10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = 5.0v t a = 25c v cc = 5.0v t a = 25c output voltage (v) 0.0 3.75 5.0 2.5 1.25 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) 0.0 3.75 5.0 2.5 1.25 output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 v cc = 5.0v t a = 25c v cc = 5.0v t a = 25c capacitance (pf) 0750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change d t aa vs. output capacitive loading v cc = 4.5v
6 5 $ 0 $ 6 & $ 6 & ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ' ', ,' ' $ $ 3dfndjhglphqvlrqv $6& rughulqjfrghv $6& sduwqxpehulqjv\vwhp package \ access time 10 ns 12 ns 15 ns 20 ns plastic soj, 400 mil AS7C513-10jc as7c3513-10jc AS7C513-12jc as7c3513-12jc AS7C513-15jc as7c3513-15jc AS7C513-20jc as7c3513-20jc tsop ii, 18.410.2 mm AS7C513-10tc as7c3513-10tc AS7C513-12tc as7c3513-12tc AS7C513-15tc as7c3513-15tc AS7C513-20tc as7c3513-20tc as7c x 513 Cxx x c sram prefix voltage:blank = 5v cmos 3 = 3.3v cmos device number access time package: j = soj 400 mil t = tsop ii, 18.410.2 mm commercial temperature range, 0c to 70 c 44-pin tsop ii min (mm) max (mm) a 1.2 a 1 0.05 a 2 0.95 1.05 b 0.25 0.45 c 0.15 (typical) d 20.85 21.05 e 10.06 10.26 h e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 d h e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l a 1 a 2 e 44-pin tsop ii 0C5 21 24 22 23 e a b 44-pin soj 400 mil min max a 0.128 0.148 a1 0.025 - a2 1.105 1.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.120 1.130 e 0.370 nom e1 0.395 0.405 e2 0.435 0.445 e 0.050 nom e d e1 pin 1 b b a1 a2 c e seating plane e2 a 44-pin soj
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